1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the correction of errors which occur within bit values held in a cache memory, such as, for example, soft errors caused by ionising radiation.
2. Description of the Prior Art
It is known to provide data processing systems with cache memories for the reason of improving processing performance. These cache memories are typically becoming greater in storage capacity and together with the other elements within integrated circuits are tending to be fabricated using smaller circuit geometries. As a consequence of this, cache memories are becoming increasingly prone to so called “soft errors”, such as those which may occur due to the impact or passage of ionising radiation. Such soft errors cause inappropriate change in one or more bit values stored within the cache memory.
Errors of this type can be particularly significant in critical and/or safety related systems, e.g. within the processor controlling an anti-lock braking system. Within such systems, high degrees of reliability are required and should be demonstrable.
One known system for handling soft errors within cache memories is described in U.S. Pat. No. 6,332,181. In this system detection of an error results in triggering of a software error handling mechanism. In the context of a critical system in which this type of error detecting and error correcting mechanism is desirable, the slowness of a software mechanism for handling such errors is a significant disadvantage, e.g. an anti-lock braking system or engine management system might be disable from its normal function for several hundred or thousand processing cycles while such an error is dealt with in software.